Design of Fault-Tolerant Nanoelectronic Architectures for Low-Power Computing Applications

Abstract

This further nanoelectronic scaled down to the deep submicron has caused greater susceptibility to soft errors, process variations, and power leakage- which an excellent fault-tolerant design strategy is required. This paper presents the researchers and the comparison of three architectures of low-power optimization: (1) a Triple Modular Redundancy ( TMR ) -based Arithmetic Logic Unit ( ALU ), (2) an Error Correction Code ( ECC ) -based ALU with Hamming (7,4) logic, and (3) a dynamically reconfigurable ALU that supports Built-In Self-Test ( BIST ) and a redundant logic block. The synthesis and simulation of all designs were done in 65nm CMOS based standard digital design processes. Several measures of performance such as power consumption, area utilization, delay and fault coverage are fully analyzed. Error masking was 99.9 percent with the TMR-based design taking on a 2.8x area overhead and consuming 45 percent more power than a non-redundant design. An ECC-based architecture found the best trade off with 86% fault coverage and little power overhead. The reconfigurable design changed fault-mitigation dynamically only when errors were detected, and thus made an energy-versus-reliability trade-off scalable. The results form the basis of scalable resilience of future nanoelectronic systems. Future research is to examine AI-assisted fault-minimization forecasting and post-CMOS fusion.