Design, Simulation, and Hardware Validation of Ultra-Low Power Embedded Architectures for IoT Edge Devices

Abstract

The spurt in deployments of Internet of Things (IoT) in energy-constrained locations made it even more pressing to have an ultra-low-power embedded structure that will guarantee a consistent operation without any sacrifice to the performance of the computation process. This paper demoes the design, simulation, and assessment of an energy-optimized embedded system architectures to work within the constraints of power-limited IoTs like environmental monitoring, biomedical telemetry and smart infrastructure control. The suggested architectures involve a set of power efficiency measures, such as dynamic voltage and frequency scaling (DVFS), subthreshold functionality and transient sleep mode levels. Core-level simulations were performed with SystemC and ARM Cortex-M microcontroller models and the performance of the simulation were measured based on the computational throughput, execution latency and energy per instruction (EPI). It has been simulated that up to 65 percent savings in energy can be achieved compared to normal settings without compromising the accuracy of the tasks and real-time responsiveness. An STM32L4 based wireless sensor node prototype was used to validate the design wherein a good match between simulated and actual performance parameters was observed. Its results highlight the importance of hardware-software co-design, peripheral power gating and low-leakage memory techniques in achieving efficiency of embedded systems. The framework allows the scaling and low power designs of 5G IoT edge intelligence, and offers a blueprint to future adaptive, AI-based energy management configuration in heterogeneous deployment usage.