Design and Optimization of a High-Efficiency Power Amplifier for Low-Power IoT Devices in Sub-GHz Wireless Applications

Abstract

The introduction of increased Internet of Things (IoT) nodes in low-energy environments has boosted the need of low-power-consumption RF front-end designs, especially in the sub-GHz band, where the long-range, low-data-rate capability would be deployed. The paper introduces a Class-E Power-Amplifier (PA) design, simulation, and optimization concept, aimed at low-power IoT-node in the ISM band frequency at 868 MHz and 915 MHz. The amplifier is fabricated in a 180 nm CMOS process; the design techniques used to maximize power-added efficiency (PAE) are impedance matching, harmonic suppression, and load-pull optimization strategies. The amplifier was also simulated and verified on Advanced Design System (ADS) at the circuit level; post-layout verification was performed in Cadence Virtuoso; including parasitic-aware models. The proposed PA has a maximum output power of +17.2 dBm and PAE of 68.5%. All its specifications, including its ability to comply with modulation schemes, like GFSK and LoRa, need to adhere to spectral and linearity requirements. The quantified EVM was acceptable to the LPWAN communication.The findings justify the scaled-down PA solution that is silicon-efficient in terms of an edge device used in the internet of things and supports low power consumption and looooong battery life at sub-GHz frequencies such as LoRa, Sigfox, and NB-IoT.