M. Mejail, B.K. Nestares, L. Gravano, E. Tacconi, G.R. Meira, A. Desages. Design and Performance Evaluation of a Hardware-Accelerated VLSI Architecture for Deep Neural Network Inference. Electronics Communications, and Computing Summit [Internet]. 2025 Dec. 7 [cited 2026 Feb. 25];3(4):19-27. Available from: https://www.eccsubmit.com/index.php/congress/article/view/227