Design and Analysis of Fault-Tolerant Architectures in Nanoelectronic Circuits - Namrata Mishra (Electronics, Communications, and Computing Summit, 2024)
The reliability of nanoelectronic circuits have become a design concern as CMOS technology scales down into the nanometer world. Modern nanoelectronic systems, with smaller transistor dimensions, lower supply voltages and increased levels of integration, are becoming ever more vulnerable to a broad range of faults such as soft errors caused by radiation, variability and aging caused by the process and transient interference. Such reliability concerns present major challenges in lot applications in aerospace, healthcare, autonomous systems and other safety-critical applications where systems must be able to tolerate any faults in the circuit.The research will look into the design and performance assessment of nanoelectronic fault-tolerant architecture configured and designed to work effectively at the most advanced technology nodes. This is to determine architectural techniques that attain a high fault coverage at small area, power, and performance overheads. Our effort is put on 3 major fault mitigation schemes, viz. Triple Modular Redundancy (TMR), Error-Correcting Codes (ECC), and dynamically configured logic blocks. The ALU is chosen as an arithmetic logic unit to be implemented; a 4-bit arithmetic logic unit (ALU) is chosen as the benchmark to obtain an estimation of the area at the industry- compatible design levels; the 7nm FinFET technology node is chosen as the implementation target using commercially available EDA tools such as Synopsis Design Compiler and Cadence Enterprise Spectre. The fault injection is used to model the effect of single-event upsets (SEUs) and permanents faults.The fault coverage analysis shows that the maximum fault coverage (99.3 percent) can be achieved by TMR with an area (200 percent) and power (320 fred disappearing muW) penalty. a more effective approach proposed by ECC has a fault coverage of 96.8% and area overhead of 60 percent. The reconfigurable logic solution is power and area efficient with 98.1 percent coverage, as well as resource-efficient in terms of reliability. Besides, the surveys of comparison case studies (on FinFET and GAAFET architectures, they show that GAAFET-based implementations have better soft-error resilience).It is indicated that there is a likelihood of research being developed to create reliable nanoelectronics with hybrid fault-tolerant techniques, especially reconfiguration and ECC-based schemes. The paper ends with providing design recommendations on future low power, high reliability integrated circuits in nanoscale technologies.