Artificial Intelligence-Driven Design Automation Framework for Efficient VLSI System Development - Pushplata Patel (Electronics, Communications, and Computing Summit, 2024)
The increasing levels of sophistication in the VERY-LARGE-SCALE INTEGRATION (VLSI) demands progressive automation techniques that can outdo the traditional heuristic-based methods. The research paper presents a modular enhanced design with intelligent architecture to incorporate machine learning (ML) at various phases of electronic design automation (EDA) process. Namely, reinforcement learning (RL) is applied to adaptive floor planning and placement, the convolutional neural networks (CNNs) aid locating the key layout patterns, and the gradient-boosted decision trees (GBDT) allow one to precisely estimate the power and delays. The proposed system than a static design flow provides continual learning throughout the iterative design iteration process, and enables a progressive refinement of performance. Experimental results to standard VLSI benchmarks, such as ISCAS-85, MCNC, and Open Cores show up 42 percent fewer time to closure a design, an 18 percent lesser power use, and much more remarkable time yield bettering when compared to baseline EDA applications. The findings point to the smart exploration of power, performance, and area (PPA) trade-offs with a strong time-to-market requirement. Moreover, its modular design guarantees the easy portability in ASIC and FPGA design implementations. In general, the method provides a framework of the next generation, AI-aided VLSI design and automation, which is both performance-sensitive and application-scalable.